Moore's law predicts that the number of transistors that can be placed on an integrated circuit (IC) is doubled approximately every two years. However, as the number of transistors increases and their size decreases, the variation in their characteristics and the probability for defects increases proportionally. For example, in nanometer-scale manufacturing processes, slight variations in the structure of a transistor can produce substantial differences in its operation with respect to other instances of the same transistor in the IC. Thus, ICs having large numbers of repeated structures, such as cells in static random access memories (SRAMS), may have defects due to manufacturing variations. These defects may impact the performance and manufacturing yield of ICs.
Repeated structures used in integrated circuits (“ICs”) may be logic elements (hereinafter referred to as “cells”), such as memory elements and gate arrays, for example. Current IC design methods assume that all cells in a repeated structure IC have the same probability of failure. For example, static random access memory (SRAM) devices, dynamic random access memory (DRAM) and phase change memory (PCM) devices may include billions of memory cells. While each instance of a cell generally has the same design, manufacturing variations may cause some of the cells to be weaker than others. That is, a weaker cell may have operational characteristics significantly below a nominal reliability parameter. For example, a weaker memory cell may have an error rate for one or more it operational characteristics (i.e., readability, writability, and stability) that is significantly above an expected (e.g., average) error rate.
The probability that a particular cell differs from the manufacturing average cell can be measured by a sigma value (x). For example, in a million cell SRAM, one would expect to find approximately 1350 cells that exhibit 3-sigma (or worse) stability properties, but only 32 cells that would exhibit 4-sigma or worse stability properties. In current technology, most SRAMs are designed to tolerate approximately 3 failing cells out of 10 million (i.e. 5-sigma), where the failing mechanism can be due to hard failures (manufacturing defects), or due to soft failures (readability, stability or writability malfunctions) all of which are voltage, temperature and process dependent. Usually increasing the voltage improves the readability, stability and writability of these weak cells, but doing so, greatly increases the overall power consumption and makes it harder (and more expensive) to maintain the temperature within design limits.
To guard against failures in weak cells, current IC designs are configured to operate using assist measures, such as higher operating voltage and/or slower speed. For example, the current design practice for SRAMs is to treat all cells as if they are 5.2-sigma weak for readability, writability, and stability. As a result, 99.9999% of the cells in an SRAM can be overdesigned, which consumes more power and performs at a slower speed. Further, 88% of memory banks will not see an SRAM cell that is worse than 4.5-sigma even in the worst case.
Because a vast majority of the SRAM cells are robust and can be expected to reliably operate without the assist measures (e.g., power assist, readability assist, writability assist, and/or stability assist), the performance (e.g., power consumption and/or speed) of the IC is unnecessarily limited by providing such measures to robust cells. Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.